1. Field of the Invention
The present invention relates to an information processing apparatus and a phase control method of controlling the phases of clocks that are supplied to redundant systems to synchronize the clocks, and more particularly to an information processing apparatus and a phase control method capable of flexibly carrying out phase control in high precision.
2. Description of the Related Art
In a network requiring high reliability, a communication route is made redundant, and a communication device having a redundant configuration is employed to constitute the network. The communication device having a redundant configuration has, for example, a duplex configuration including a current system and a standby system. When a trouble occurs in the configuration of the current system, the network relays the process to the configuration of the standby system, thereby avoiding an interruption of communications.
In the communication device having the duplex configuration, reference clocks that control the operation timing of various kinds of process are independently supplied to the current system and the standby system to increase the availability. However, when there is a phase difference between the phase of the reference clock supplied to the current system and the phase of the reference clock supplied to the standby system, a transmission/reception error of a main signal occurs at the time of changeover between the current system and the standby system, and the communication line is momentarily disconnected.
To prevent the occurrence of this trouble, it is necessary to correct the phase difference between the phases of the reference clocks supplied to the redundant systems and accurately synchronize the reference clocks. Conventional techniques of correcting a phase difference between phases of reference clocks are disclosed in Japanese Patent Application Laid-open No. S62-269434 and Japanese Patent Application Laid-open No. H10-240375.
Japanese Patent Application Laid-open No. S62-269434 discloses the following technique. A return loop is provided to return a reference clock transmitted from a supplier to a supply destination, to a supplier. A length of a cable connected between the supplier and the supply destination is obtained based on a result of measuring a loop resistance of a return loop, thereby adjusting a delay amount given to the reference clock.
Japanese Patent Application Laid-open No. H10-240375 discloses the following technique. Fixed delay units, each having a different delay amount, are provided at plural stages in a reference-clock supply destination. A reference clock, output from a fixed delay unit, having the smallest phase difference between a phase of a reference clock of a current system and a phase of a reference clock of a standby system is selectively used.
However, recently, the speed of the reference clock has been increased along with the increase in the communication speed. Therefore, according to the method of adjusting a delay amount by obtaining a cable length based on a result of measuring a loop resistance like the technique disclosed in Japanese Patent Application Laid-open No. S62-269434, it is difficult to adjust the delay amount in sufficient precision.
Further, according to the method using the fixed delay unit like the technique disclosed in Japanese Patent Application Laid-open No. H10-240375, it is not possible to flexibly cope with a phase difference between the phases of the reference clocks generated due to various factors such as a tolerance of a cable length and individual differences of various kinds of mounted parts. Therefore, a correctable range of the phase difference is limited.